J o b N i n j a

616581 #

****

אימייל:

****

טלפון ראשי:
****
מיקום:

****

גיל:

לא צויין

מין:

לא צויין

מצב משפחתי:

לא צויין

טלפון נוסף:

****

היקף משרה מבוקש:

אין פרטים זמינים

זמינות:

אין פרטים זמינים

השכלה:

תיכונית, מקצועית

שפות :

עברית

אנגלית

רישיון:

אין פרטים זמינים

רכב:

רכב פרטי

פרופיל תעסוקתי:



Electronics engineer specializing in FPGA and RTL design with functional verification experience.
Hands-on experience with SystemVerilog, constrained-random testing, and coverage-driven
environments.
Graduate of the Technion Chip Design & Verification Program, developing RTL modules and FPGAoriented verification projects using Synopsys VCS.
Education
Chip Design & Verification Course, Technion - Completed Oct 2025
Key Topics: RTL Design, Functional Verification, SystemVerilog, UVM Concepts, ConstrainedRandom Testing, Functional Coverage, EDA Tools (Synopsys VCS, Cadence)
Projects: ALU with Memory | Frame Aligner | DDR Interface Simulation .
B.Sc. Electrical Engineering, Ariel University, 2020–2024
Specialization: Computers and VLSI
Relevant coursework: Digital Logic Design, Computer Architecture, RTL Synthesis,
Microprocessors, and VLSI Design Labs .
Technical Skills
SystemVerilog | Verilog | UVM Concepts | RTL Design | Functional Verification | Constrained-Random
Testing | Coverage | Debug & Waveform Analysis | Synopsys VCS | Cadence Tools | Python (Basics)
Projects
• ALU + Memory (RTL Design & Verification) – Developed a SystemVerilog testbench with
generator, monitors, and scoreboard for a parameterized ALU with integrated memory.
Applied constrained-random stimulus and coverage tracking using a UVM-like structure.
• Frame Aligner (FSM Design & Verification) – Built a class-based verification environment
from scratch for FSM-based frame alignment logic.
Implemented event-driven checking and functional coverage tracking for data
synchronization and header detection.
• DDR Interface Simulation – Modeled and verified DDR protocol timing, latency, and
coverage metrics using randomized traffic.



Work Experience
Electronics Engineering Intern – Sensor Measurement System |Linok-Tech , 2025:
• Assisted in integrating and testing a multi-sensor measurement system (AS7265X, INA3221,
PT100)
• Supported firmware debugging and SPI/I²C interface validation.
• Conducted calibration checks and analyzed sensor output accuracy.
Military Service
• Combat soldier, Egoz Unit (2016–2019) . Commander, Sayeret Matkal basic training .
Languages
Hebrew: Native | English: Professional Working Proficiency.

הערות: 

Loading...
Loading...